About Me
- He is currently a Ph.D. candidate at Shanghai Jiao Tong University, Dept. of Computer Science and Engineering, SEIEE. He is supervised by Prof. Jingwen Leng, and he mainly researches on computer architecture, AI system, compiler and optimization. He has broad interests including chip design, compiler optimization, computer organization and system architecture. Learn more on his CV.
Contact
- E-mail: altair DOT liu AT sjtu DOT edu DOT cn
- DBLP Page, Google Scholar Page, ORCID
Education
| Duration | Degree | Dept. | Affiliation |
|---|---|---|---|
| 2015.09-2019.07 | Bachelor | Dept. of Computer Science and Software Engineer | East China Normal University |
| 2019.09-2022.03 | Master | Dept. of Computer Science and Engineering | Shanghai Jiao Tong University |
| 2022.03-2025.09 | Ph.D | Dept. of Computer Science and Engineering | Shanghai Jiao Tong University |
Job
| Duration | Title | Dept. | Affiliation | Job Description |
|---|---|---|---|---|
| 2018.08- 2019.01 |
Intern | IBSO | SAP | Cloud Foundry development |
| 2019.02- 2019.06 |
Intern | GPU SM Arch | NVIDIA | CModel development |
| 2020.06- 2021.06 |
Intern | IAGS | Intel | LLVM CodeGen |
| 2021.07- 2022.05 |
Research Intern | Shanghai Qi Zhi Institute | Research | |
| 2022.06- 2022.12 |
Intern | GFX HW MI | AMD | GPU IP DV(Design Verification) |
Publications
- [HPCA’25] Zihan Liu, Xinhao Luo, Junxian Guo, Wentao Ni, Yangjie Zhou, Yue Guan, Cong Guo, Weihao Cui, Yu Feng, Minyi GUo, Yuhao Zhu, Minjia Zhang, Jingwen Leng, Chen Jin. VQ-LLM: High-performance Code Generation for Vector Quantization Augmented LLM Inference.
[LLM, Quantization, Code Generation] - [HPCA’25] Weiming Hu, Haoyan Zhang, Cong Guo, Yu Feng, Renyang Guan, Zhendong Hua, Zihan Liu, Yue Guan, Minyi Guo, Jingwen Leng. MANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type.
[LLM, Quantization, Accelerator] - [TACO’24] Yu Feng, Weikai Lin, Zihan Liu, Jingwen Leng, Minyi Guo, Han Zhao, Xiaofeng Hou, Jieru Zhao, Yuhao Zhu. Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture.
[NeRF, Accelerator] - [ISCA’24] Yu Feng, Zihan Liu, Jingwen Leng, Minyi Guo, Yuhao Zhu. Cicero: Addressing Algorithmic and Architectural Bottlenecks in Neural Rendering by Radiance Warping and Memory Optimizations.
[NeRF, Accelerator] - [ASPLOS’24] Zihan Liu, Wentao Ni, Jingwen Leng, Yu Feng, Cong Guo, Quan Chen, Chao Li, Minyi Guo, Yuhao Zhu. JUNO: Optimizing High-Dimensional Approximate Nearest Neighbour Search with Sparsity-Aware Algorithm and Ray-Tracing Core Mapping.
[Nearest Neighbor, Ray Tracing] - [ASPLOS’24] Cong Guo, Rui Zhang, Jiale Xu, Jingwen Leng, Zihan Liu, Ziyu Huang, Minyi Guo, Hao Wu, Shouren Zhao, Junping Zhao, Ke Zhang. GMLake: Efficient and Transparent GPU Memory Defragmentation for Large-scale DNN Training with Virtual Memory Stitching.
[LLM, GPU Memory] - [CF’23] Yangjie Zhou, Yaoxu Song, Jingwen Leng, Zihan Liu, Weihao Cui, Zhendong Zhang, Cong Guo, Quan Chen, Li Li, Minyi Guo. AdaptGear: Accelerating GNN Training via Adaptive Subgraph-Level Kernels on GPUs.
[GNN, Code Generation] - [MICRO’22] Cong Guo, Chen Zhang, Jingwen Leng, Zihan Liu, Fan Yang, Yunxin Liu, Minyi Guo, Yuhao Zhu. ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization.
[LLM, Quantization, Accelerator] - [ASPLOS’22] Zihan Liu, Jingwen Leng, Zhihui Zhang, Quan Chen, Chao Li, Minyi Guo. VELTAIR: Towards High-Performance Multi-tenant Deep Learning Service via Adaptive Compilation and Scheduling.
[Code Generation, DNN Runtime] - [ISPA’20] Zihan Liu, Jingwen Leng, Quan Chen, Chao Li, Wenli Zheng, Li Li, Minyi Guo. DLFusion: An Auto-Tuning Compiler for Layer Fusion on Deep Neural Network Accelerator.
[Compiler] - [CCF-THPC’20] Zihan Liu, Jingwen Leng, Guandong Lu, Chenhui Wang, Quan Chen, Minyi Guo. Survey and design of paleozoic: a high-performance compiler tool chain for deep learning inference accelerator.
[Compiler]
Project Experience
- R&D Project: LLM Quantization and accelerator architecture research, 2023-2024.
- R&D Project: Compiler stack prototype of hetergeneous DNN accelerator, 2021.
- National Key Research Project: Compiler stack of MLU-100 accelerator, 2019-2020.
- Course and miscs.: C-alike language, Turing GPU disserting and profiling, …
Skills
- C, C++, CUDA/PTX, Triton
- Verilog, verilator
- TVM, MLIR, LLVM
- LaTeX, git, vim, Linux, …
Miscs.
Interests: Games (ACT, FPS, Flight Simulation, ACG), Saxophone, Archery, Astrophotography, Badminton.
